EDAN15 - Design of Embedded Systems

EDAN15 - Design of Embedded Systems

Course modules

Part 1: Introduction (18/3, 22/3)

Part 1: Introduction (18/3, 22/3)
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Part 1: Introduction (18/3, 22/3) 191821  
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    Course Plan, Administrative Information Course Plan, Administrative Information
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    A Motivation: Embedded Systems in Industry A Motivation: Embedded Systems in Industry
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    Building Blocks Building Blocks
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    Processing Elements Processing Elements
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    Parallelism Parallelism
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    Memory Memory
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    Input & Output; Sensors & Actuators Input & Output; Sensors & Actuators
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    Software for Embedded Systems Software for Embedded Systems
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    Requirements and Constraints; Choosing Components Requirements and Constraints; Choosing Components
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  • Assignment
    Lab 1: Getting Started with LinguaFranca Lab 1: Getting Started with LinguaFranca
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  • Discussion topic
    Q&A Q&A
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    Recommended Exercises 0 Recommended Exercises 0
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Part 2-3: Modeling (25/3, 28/3, 15/4)

Part 2-3: Modeling (25/3, 28/3, 15/4)
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Part 2-3: Modeling (25/3, 28/3, 15/4) 191822  
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    Introduction to Models of Computation Introduction to Models of Computation
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    Finite State Machines Finite State Machines
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    Concurrent Models of Computation Concurrent Models of Computation
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    Synchronous Reactive Models Synchronous Reactive Models
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    Timed Models Timed Models
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  • Assignment
    Lab 2: Vending Machine in LF Lab 2: Vending Machine in LF
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  • Assignment
    Lab 3: Timing in the Vending Machine Lab 3: Timing in the Vending Machine
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  • Discussion topic
    Q&A Q&A
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    Recommended Exercises I Recommended Exercises I
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Part 4: Design (19/4, 22/4)

Part 4: Design (19/4, 22/4)
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Part 4: Design (19/4, 22/4) 191823  
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    Design overview Design overview
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    Scheduling Scheduling
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    Mapping Mapping
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  • Assignment
    Lab 4: Deterministic Concurrency via LF Lab 4: Deterministic Concurrency via LF
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  • Discussion topic
    Q&A Q&A
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    Recommended Exercises II Recommended Exercises II
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Part 5: Analysis & Verification (26/4, 29/4)

Part 5: Analysis & Verification (26/4, 29/4)
Module completed Module in progress Module locked
Part 5: Analysis & Verification (26/4, 29/4) 191824  
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    Invariants and Temporal Logic Invariants and Temporal Logic
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    Equivalence and Refinement Equivalence and Refinement
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    Quantitative Analysis Quantitative Analysis
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  • Assignment
    Lab 5: Simple Analysis Lab 5: Simple Analysis
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  • Discussion topic
    Q&A Q&A
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    Recommended Exercises III Recommended Exercises III
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Outro

Outro
Module completed Module in progress Module locked
Outro 191825  
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    Exam Preparation Exam Preparation
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minimum score must view must submit must contribute